NEWS

As the semiconductor industry continues to evolve toward higher performance, higher density, and miniaturization, the traditional path of scaling down chip device dimensions to enhance computing power and performance—driven by Moore’s Law—is increasingly approaching physical limits and process bottlenecks. With transistor processes moving into 3nm, 2nm, and even more advanced nodes, scaling alone not only entails extremely high R&D and manufacturing costs but also introduces technical issues such as leakage current, uneven heat dissipation, and reduced stability, making it difficult to meet the extreme demands for comprehensive chip system performance in cutting-edge fields like artificial intelligence, high-performance computing, high-end servers, and high-speed communications. Against this industry backdrop, chip manufacturers are moving beyond traditional process iteration thinking and shifting their innovation focus to backend areas such as packaging and system integration. As a result, advanced packaging technology has emerged as a core innovation track to break through performance bottlenecks and sustain semiconductor industry upgrades.

As the central enabler of advanced packaging technology evolution, the material properties of the packaging substrate directly determine the interconnection precision, form factor, operational stability, and service life of chip packaging, making it a critical factor in the realization of high-end packaging solutions. Current mainstream packaging substrates are primarily based on materials such as resin and ceramics. While these mature materials are suitable for low- to mid-end packaging processes, their limitations become evident in ultra-large-scale, ultra-high-density high-end packaging scenarios. Common issues include low interconnection precision ceilings, relatively high coefficients of thermal expansion, insufficient dimensional stability, and severe warpage in large-scale processing—all of which fail to meet the development needs of high-end chips requiring multi-chip integration, high-density interconnects, and large-scale packaging.

To overcome the technical shortcomings of traditional substrate materials and align with the advancement of advanced packaging, glass core substrates have emerged as a next-generation high-end packaging solution being actively evaluated, developed, and deployed by the global semiconductor industry, leveraging their unique physical properties and process advantages. Compared with traditional substrate materials such as resin and ceramics, glass core substrates offer several disruptive advantages that holistically enable high-end packaging technology upgrades. First, their excellent structural characteristics support larger-scale integrated packaging, meeting the demands of multi-chip integration and high-compute module assembly, thereby significantly improving chip system integration and overall computing power. Second, the high surface flatness and excellent dielectric uniformity of glass materials enable finer and higher-density interconnect routing, effectively reducing line spacing, enhancing signal transmission efficiency, and minimizing loss and delay in high-speed signal transmission—perfectly suited for the performance requirements of high-speed computing and high-frequency communication chips. Finally, glass core substrates feature an extremely low coefficient of thermal expansion, providing exceptional dimensional stability. During high-temperature packaging processes and long-term operation under alternating high and low temperatures, they are less prone to deformation or warpage, thereby improving packaging yield and enhancing chip operational reliability and stability.

Currently, glass core substrate technology has entered the critical stage of process validation and small-batch testing. With continued industry investment in R&D and the ongoing maturation of manufacturing processes, the pace of large-scale adoption is expected to accelerate. Glass core substrates are poised to become a core material for future high-end advanced packaging, providing essential support for the semiconductor industry to overcome performance bottlenecks and achieve technological innovation and upgrades.